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HV219 Low Charge Injection 8-Channel High Voltage Analog Switch
Features
HVCMOS(R) technology for high performance Very low quiescent power dissipation -10A Output ON-resistance typically 11 Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Serial shift register logic control with latches Flexible operating supply voltages Surface mount packages
General Description
The Supertex HV219 is a low switch resistance, low charge injection 8-channel 200V analog switch integrated circuit (IC) intended primarily for medical ultrasound imaging. The device can also be used for NDE, non-destructive evaluation applications. The HV219 is a lower switch resistance, 11 versus 22, version of the Supertex HV20220 device. The lower switch resistance will help reduce insertion loss. It has the same pin configuration as that of the Supertex HV20220PJ and the HV20220FG. The device is manufactured using Supertex's HVCMOS(R) (high voltage CMOS) technology with high voltage bilateral DMOS structures for the outputs and low voltage CMOS logic for the input control. The outputs are configured as eight independent single pole single throw 11 analog switches. The input logic is an 8-bit serial to parallel shift register followed by an 8-bit parallel latch. The switch states are determined by the data in the latch. Logic high will correspond to a closed switch and logic low as an opened switch. The HV219 is designed to operate on various combinations of high voltage supplies. For example the VPP and VNN supplies can be: +40V/-160V, +100V/-100V, or +160V/-40V. This allows the user to maximize the signal voltage for uni-polar negative, bi-polar, or unipolar positive.
Level Output Latches Shifters Switches
D LE CL
Applications
Medical ultrasound imaging Non-destructive evaluation
Block Diagram
DIN
SW0
D LE CL
SW1
CLK
D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL
SW2
8-Bit Shift Register
SW3
SW4
SW5
DOUT
SW6
SW7
VDD GND LE CL
VNN VPP
HV219
Ordering Information
Package Options Device HV219 28-Lead PLCC HV219PJ HV219PJ-G 48-Lead LQFP (7x7x1.4mm) HV219FG HV219FG-G
Pin Configurations
4 1 25
-G indicates the part is RoHS compliant (Green)
28-Lead (J) PLCC (PJ)
(top view)
Absolute Maximum Ratings
Parameter VDD logic power supply voltage VPP - VNN supply voltage VPP positive high voltage supply VNN negative high voltage supply Logic input voltages Analog signal range Peak analog signal current/channel Storage temperature Power dissipation: 28-Lead PLCC 48-Lead LQFP (7x7x1.4mm) Value -0.5V to +15V 220V -0.5V to VNN +200V +0.5V to -200V -0.5V to VDD +0.3V VNN to VPP 3.0A -65OC to +150OC 1.2W 1.0W
48 1
48-Lead LQFP (FG) (7x7x1.4mm)
(top view)
Product Marking
Top Marking
YYWW
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
HV219PJ
LLLLLLLLLL
Operating Conditions
Symbol Parameter VDD VPP VNN VIH VIL VSIG TA Logic power supply voltage Positive high voltage supply Negative high voltage supply High level input logic voltage Low-level input logic voltage Analog signal voltage peak-to-peak Operating free air temperature Value 4.5V to 13.2V 40V to VNN +200V -40V to -160V VDD -1.5V to VDD 0V to 1.5V VNN +10V to VPP -10V 0OC to 70OC
Bottom Marking
CCCCCCCCCCC AAA
YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = "Green" Packaging
*May be part of top marking.
28-Lead PLCC (PJ)
Top Marking
YYWW
HV219FG
LLLLLLLLL
Bottom Marking
CCCCCCCC AAA
YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = "Green" Packaging
*May be part of top marking
48-Lead LQFP (FG)
2
HV219
DC Electrical Characteristics (over recommended operating conditions unless otherwise noted)
Sym Parameter 0OC Min RONS Small signal switch On-resistance RONS RONL ISOL Small signal switch On-resistance matching Large signal switch On-resistance Switch off leakage per switch DC offset switch off DC offset switch on IPPQ INNQ IPPQ INNQ Quiescent VPP supply current Quiescent VNN supply current Quiescent VPP supply current Quiescent VNN supply current Switch output peak current fSW Output switch frequency IPP Average VPP supply current INN Average VNN supply current IDD IDDQ ISOR ISINK CIN Average VDD supply current Quiescent VDD supply current Data out source current Data out sink current Large input capacitance 0.45 0.45 Max 15 13 13 9 12 11 20 5.0 300 500 3.0 6.5 4.0 4.0 6.5 4.0 4.0 4.0 10 10 Min 0.45 0.45 3
+25OC Typ 13 11 11 9 10 8 5.0 8 1.0 100 100 10 -10 10 -10 3.0 0.70 0.70 Max 19 14 14 12 13 13 20 10 300 500 50 -50 50 -50 2.0 50 7.0 5.0 5.0 7.0 5.0 5.0 4.0 10 10
+70OC Min 0.40 0.40 Max 24 16 15 14 15 14 20 15 300 500 2.0 8.0 5.5 5.5 8.0 5.5 5.5 4.0 10 10
Units Conditions ISIG = 5mA VPP = +40V VNN = ISIG = 200mA 160V ISIG = 5mA VPP = +100V ISIG = 200mA VNN = 100V
VPP = +160V ISIG = 200mA V = -40V NN ISIG = 5mA % A mV mV A A A A A kHz ISIG = 5mA, VPP = +100V, VNN = -100V VSIG = VPP - 10V, ISIG = 1A VSIG= VPP -10V & VNN +10V RLOAD = 100K RLOAD = 100K All switches off All switches off All switches on, ISW = 5mA All switches on, ISW = 5mA VSIG duty cycle < 0.1% Duty cycle = 50% VPP = +40V VNN = -160V mA VPP = +100V VNN = -100V All output VPP = +160V switches are turning VNN = -40V ON and VPP = +40V OFF at VNN = -160V 50kHz with VPP = +100V no load VNN = -100V VPP = +160V VNN = -40V mA A mA mA pF fCLK = 5MHz, VDD = 5.0V All logic inputs are static VOUT = VDD - 0.7V VOUT = 0.7V ---
mA
HV219
AC Electrical Characteristics (over recommended operating conditions, V
Sym tSD tWLE tDO twCL tSU tH fCLK tr, tf TON TOFF Parameter Set-up time before LE rises Time width of LE Clock delay time to data out Time width of CL Set-up time data to clock Hold time data from clock Clock frequency Clock rise and fall times Turn-on time Turn-off time 0OC Min 150 150 150 15 35 dv/dt Maximum VSIG slew rate KO KCR IID Off isolation Switch crosstalk Output switch isolation diode current -30 -58 14 40 Output voltage spike Q Charge injection Max 150 5.0 50 5.0 5.0 20 20 20 300 25 60 Min 150 150 150 15 35 -30 -58 -60 14 40 +25OC Typ 8.0 -33 20 50 1450 1050 550 Max 150 5.0 50 5.0 5.0 20 20 20 300 25 60 150 200 150 200 150 200 Min 150 150 150 20 35 14 40 DD
= 5.0V, unless otherwise noted)
+70OC Max 150 5.0 50 5.0 5.0 20 20 20 300 25 60 -
Units Conditions ns ns ns ns ns ns MHz ns s s ------------50% duty cycle, fDATA = fCLK/2 --VSIG = VPP -10V, RLOAD = 10K VSIG = VPP -10V, RLOAD = 10K VPP = +40V, VNN = -160V V/ns VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V dB dB mA pF pF F = 5MHz, 1K//15pF load F = 5MHz, 50 load F = 5MHz, 50 load 300ns pulse width, 2% duty cycle 0V, f = 1MHz 0V, f = 1MHz VPP = +40V, VNN = -160V, RLOAD = 50 mV VPP = +100V, VNN = -100V, RLOAD = 50 VPP = +160V, VNN = -40V, RLOAD = 50 VPP = +40V, VNN = -160V, VSIG = 0V pC VPP = +100V, VNN = -100V, VSIG = 0V VPP = +160V, VNN = -40V, VSIG = 0V
CSG(OFF) Off capacitance SW to GND CSG(ON) +VSPK -VSPK +VSPK -VSPK +VSPK -VSPK On capacitance SW to GND
4
HV219
Truth Table
Data in 8-Bit Shift Register D0 L H L H L H L H L H L H L H L H X X X X X X X X X X X X X X X X D1 D2 D3 D4 D5 D6 D7 LE L L L L L L L L L L L L L L L L H X CL L L L L L L L L L L L L L L L L L H OFF OFF Hold Previous State OFF OFF OFF OFF OFF OFF Output Switch State SW0 OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON SW1 SW2 SW3 SW4 SW5 SW6 SW7
Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition clock. 3. The switches go to a state retaining their present condition at the rising edge of the LE. 4. When LE is low, the shift register data flows through the latch. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The clear input overrides all other inputs.
Logic Timing Waveforms
D DATA IN
N+1
DN 50% 50%
DN-1
LE
50%
50% t WLE t SD 50% 50% th t DO
CLOCK t SU
DATA OUT
50% t OFF t ON
OFF V OUT (TYP) ON
90% 10%
CLR
50% t WCL
50%
5
HV219
Test Circuits
VPP -10V RL 10K VOUT VOUT
VPP -10V
ISOL
VNN +10V
100K
RL
VPP VNN
VPP VNN
VDD GND
5V
VPP VNN
VPP VNN
VDD GND
5V
VPP VNN
VPP VNN
VDD GND
5V
Switch OFF Leakage
DC Offset ON/OFF
TON /TOFF Test Circuit
VIN = 10 VP-P @5MHz VSIG VOUT RL IID VNN
VIN = 10 VP-P @5MHz 50 NC 50
VPP VNN
VPP VNN
VDD GND VOUT VIN
5V
VPP VNN
VPP VNN
VDD GND
5V
VPP VNN
VPP VNN
VDD GND VOUT VIN
5V
KO = 20Log
KCR = 20Log
OFF Isolation
Isolation Diode Current
Crosstalk
VOUT VOUT 1000pF
+VSPK VOUT -V SPK 50
VSIG 1K RL
VPP VNN
VPP VNN
VDD GND
5V
VPP VNN
VPP VNN
VDD GND
5V
Q = 1000pF x VOUT
Charge Injection
Output Voltage Spike
6
HV219
Pin Description 28-Lead (J-Lead) PLCC (PJ)
Pin 1 2 3 4 5 6 7 Function SW3 SW3 SW2 SW2 SW1 SW1 SW0 Pin 8 9 10 11 12 13 14 Function SW0 NC VPP NC VNN GND VDD Pin 15 16 17 18 19 20 21 Function NC DIN CLK LE CL DOUT SW7 Pin 22 23 24 25 26 27 28 Function SW7 SW6 SW6 SW5 SW5 SW4 SW4
Pin Description 48-Lead LQFP (7x7x1.4mm) (FG)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 Function SW5 NC SW4 NC SW4 NC NC SW3 NC SW3 NC SW2 Pin 13 14 15 16 17 18 19 20 21 22 23 24 Function NC SW2 NC SW1 NC SW1 NC SW0 NC SW0 NC VPP Pin 25 26 27 28 29 30 31 32 33 34 35 36 Function VNN NC NC GND VDD NC NC NC DIN CLK LE CLR Pin 37 38 39 40 41 42 43 44 45 46 47 48 Function DOUT NC SW7 NC SW7 NC SW6 NC SW6 NC SW5 NC
Power Up/Down Sequence
1) Power up/down sequence is arbitrary except GND must be powered up first and powered down last. This applies for applications powering GND of the IC with different voltages. 2) VSIG must always be at or in between VPP and VNN or floating during power up/down transition. 3) Rise and fall times of the power supplies VDD, VPP, and VNN should not be less than 1.0ms.
7
HV219
28-Lead PLCC Package Outline (PJ)
.048/.042 x 45O 4 D D1 1 .056/.042 x 45O
28
26
0.150 MAX
Note 1 (Index Area) 0.075 MAX E1 E
0.20max 3 Places
Top View
View B A Base Plane .020 MIN e b Seating Plane
A1 A2
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (inches) NOM MAX
A .165 .172 .180
A1 .090 .105 .120
A2 .062 .083
b .013 .021
D .485 .490 .495
D1 .450 .453 .456
E .485 .490 .495
E1 .450 .453 .456
e .050 BSC
JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale.
8
HV219
48-Lead LQFP (7x7x1.4mm) Package Outline (FG)
D D1
E
E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 Seating Plane Gauge Plane
Top View
View B A A2 Seating Plane A1
View B
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
A 1.40 1.60
A1 0.05 0.15
A2 1.35 1.40 1.45
b 0.17 0.22 0.27
D 8.80 9.00 9.20
D1 6.80 7.00 7.20
E 8.80 9.00 9.20
E1 6.80 7.00 7.20
e 0.50 BSC
L 0.45 0.60 0.75
L1 1.00 REF
L2 0.25 BSC
0O 3.5O 7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV219 NR050807
9

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